1. Field of the Invention
The present invention relates to methods of fabricating, discrete semiconductor devices and in particular power semiconductor devices. More particularly, the present invention relates to fabricating power semiconductor diodes.
2. Background of the Invention
Power semiconductor rectifiers have a variety of applications including applications in power supplies and voltage converters. For example, an important application of such rectifiers is in DC to DC voltage converters and power supplies for personal computers and other electronic devices and systems. In such applications, it is important to provide both a fast recovery time for the semiconductor rectifier and a low forward voltage drop across the rectifier (Vf). In particular, DC to DC voltage converter applications employ switched inputs and the recovery time of the rectifier used in the voltage converter will affect the dynamic losses for a given frequency of operation of the input. Also, a fast recovery time is needed for rectification of high frequency signals which are present in computers and many other electronic devices.
A low Vf in turn is needed in low voltage applications including power supplies for computers and other low voltage (e.g., 12 volt and lower) electronics applications. In particular, computer applications will typically require both a five volt power supply and a 3.5 volt power supply and in the future it may be as low as a one volt power supply. In converting the input five volt power supply to a 3.5 volt power supply, the voltage converter will inevitably introduce a loss due to the Vf drop across the rectifier in the converter circuit. In typical fast recovery semiconductor diodes employed in such devices, the voltage drop Vf may be approximately 0.7-0.8 volts. This results in a significant percentage of available power being wasted due to the voltage drop across the rectifier. For example, as much as 40% of the available power may be wasted in a two step voltage conversion from a 5 volt input to a one volt output. As a result, a significant portion of the available power may be simply dissipated in the device due to the relatively high Vf. This wasted power is obviously significant in laptop and notebook computers and other portable devices relying on battery power. However, such wasted power is also a significant problem in desktop computers and other devices due to heat generation.
A discrete power rectifier device providing these desirable features has been disclosed in U.S. patent application Ser. No. 09/283,537 filed Apr 1, 1999. The process takes full advantage of the high degree of controllability in the modern VLSI IC manufacturing which allows a generation of very high density of conducting elements, leading to low Vf devices. At the same time, the disclosed process is highly self aligned and therefore is very cost efficient.
The importance of the latter quality can not be overestimated: any commercial production of commodity products will always be dictated by cost considerations.
A thorough examination of a structure described in the 537 Application reveals that the body concentration profile (usually B for the more common device polarity) has to satisfy at least two different requirements:
a) support high breakdown voltage and,
b) precisely control V threshold (main factor in determining Vf).
In general terms such a situation calls for the capability to create almost any possible (desirable) concentration profiles (both in Vertical as well as in Horizontal directions) which generally speaking does not conform to any standard impurity profiles generated by Ion Implantation and Annealing (Diffusion) steps.
Such capability is described in the application Ser. No. 09/283,537, where it is suggested that multiple spacers and corresponding Implants (one or more per each spacer) commensurate with different annealing steps for different implants can generate profits of almost unlimited flexibility.
In real implemented processes it turned out that two spacers, two implantation and annealing steps generate sufficient optimization.
Many Boron Implants may take many spacers, which may become prohibitively expensive (e.g. can preclude such process from being ever implemented in mass production). Although a two spacer process can be acceptable as a generator of a suitable compromise between V forward (V threshold) and V breakdown, it""s still expensive and reduces desired profit margin.
In view of the above, it will be appreciated that a need presently exists for a method of fabricating a complex IC discrete rectifier device which can reduce processing costs, which is readily compatible with available integrated circuit processing techniques and which may provide a device with a high breakdown voltage such as desired for power applications.
The present invention provides a method for manufacturing a rectifier device which is compatible with existing semiconductor technology, which provides a high degree of reliability in device characteristics and which can provide such devices at reduced cost.
In a preferred embodiment, the present invention provides a method of fabricating a rectifier device employing a reduced number of processing steps and hence reduced cost. The method employs forming a plurality of pedestals on the top surface of a semiconductor substrate which pedestals are used to align the structures forming the active cells. A gate is formed on the pedestal sidewalls and substrate adjacent to the pedestals as a thin conducting (e.g., implanted) layer on top of the gate oxide. A first spacer is formed adjacent the pedestal sidewalls, followed by a first implant into the semiconductor substrate which is laterally defined by the first spacer to form a body region. The first spacer is then removed. A second thicker spacer is then formed adjacent the pedestal sidewalls, followed by a second implant of a dopant of the first conductivity type laterally defined by the second spacer. This second implant has a depth and/or concentration which differs from that of the first implant to provide a desired depth and dopant concentration profile to the body region. A third implant is performed, also using the second spacer, of a dopant of a second conductivity type. The first and third implants define channel regions adjacent the pedestals and below the gate oxide while the first and second implants tailor the P/N junction profile with the substrate to improve breakdown resistance. The method proceeds by forming first and second electrical contact metallization layers on the top and bottom surfaces of the substrate, providing a vertical device structure having a current flow path between the surfaces.
More specifically, the use of two spacers both referenced to the pedestal sidewalls in a self aligned manner, allows the channel dimensions and dopant levels to be precisely controlled despite inevitable process variations in spacer sidewall formation. The present invention also provides a tailored body region profile using the same two spacers employed for self aligned channel formation. Therefore, a body region doping profile can be provided which increases breakdown voltage, without the need for additional spacers. Also, only two masking steps are required. These features provide significant cost advantages. An optional third masking step may be employed to form guard ring and plug regions.
Further features and advantages of the present invention will be appreciated by review of the following detailed description of the invention.